20+ years of FPGA design experience, product ranging from smaller Xilinx Spartan devices to multi-million gates Ultrascale+ MPSOC/RFSOC.

Entire ASIC flow design experience, front-end RTL development to GDSII. Product ranging from mixed-signal RFICs to larger SOCs.

Expert level Physical Design experience. Advanced nodes Place and Route, and multi power domains handling. Many successful tapeouts.

Excellence in firmware design and development, strong focus on embedded Linux and bare metal systems. Extensive firmware experience for silicon bring up and test.

  • Verilog, Systemverilog, VHDL
  • Complete system design experience
  • CPU subsystem, Gigabit Ethernet, PCIe, DMA and more
  • Power domain system analysis
  • RF/Analog interfaces, mixed-signal design
  • Linting, Formal Verification, Synthesis
  • Direct testing, OVM, UVM
  • Functional sim
  • Gate level sim with unit delay and timing
  • RTL sign-off
  • ASIC flow: RTL to GDSII
  • Foundry shuttle and full mask runs
  • Process technology
  • Memory compilers
  • CAD tools
  • File management, source control
  • Embedded Linux (Yocto, Buildroot,…)
  • Bare metal
  • BSP & Device Driver
  • Wireless & IoT
  • Macro level, Chip level
  • Mixed-signal design
  • Low Power, clock tree synthesis
  • IR drop and Power Analysis
  • 12nm-5nm experience
  • Includes OCV, AOCV
  • PrimeTime and Tempus STA Sign-off
  • Complete FPGA development flow
  • RTL, Implementation, board bringup, production
  • ASIC emulation
  • Test and production firmware development
  • Final GDSII integration
  • DRC/LVS/EMC signoff
  • Analog SPEF and SDF generation